面向VLSI的门级单粒子效应评估技术

Gate Level Single-Event Effect Evaluation Technique for VLSI

中文关键词:  单粒子效应  超大规模集成电路（VLSI）  硬件描述语言  门级  三模冗余

英文关键词:single-event effect  very large scale integration(VLSI)  hardware description language  gate level  three-mode redundancy

中文摘要:

      由于空间辐射环境充满了各类射线和高能粒子，非常容易诱发集成电路发生单粒子效应，因此有必要开发对应的评估技术，分析单粒子效应对超大规模集成电路（VLSI）的影响。以ISCAS89测试基准电路为主要研究对象，提出了一种适用于VLSI的单粒子效应评估技术，可以通过脚本自动生成仿真和测试文件，实现任意节点的故障注入，并可以在任何一种支持硬件描述语言的EDA仿真工具上进行评估。分别对使用三模冗余技术、自刷新寄存器技术加固后的电路和原始电路进行了对比评估。评估结果符合逻辑，验证了门级单粒子效应评估测试技术的有效性。通过提出的评估技术，可以快速评估电路的抗辐射能力，提高查找设计缺陷、对电路进行针对性加固的效率，对于提高集成电路的安全性和稳定性有着重要的应用价值。

英文摘要:

      Since the space radiation environment is full of various types of rays and high-energy particles,it is very easy to induce single-event effects(SEEs) in integrated circuits.Therefore,it is necessary to develop corresponding evaluation techniques to analyze the effects of single-event effects on very large scale integration (VLSI).Based on the ISCAS89 benchmark circuit,a single-event effect evaluation technology for VLSI is proposed.The simulation and test files can be automatically generated by scripts,fault injection can be performed at any circuit node,and the technology can be evaluated in any EDA simulation tool that supports hardware description language.The circuits reinforced with three-mode redundancy technology and the self-refreshing register technology were compared with the original circuits.The evaluation results are reasonable,which verify the effectiveness of the gate-level single-event effect evaluation technology.The proposed technology can evaluate the SEE-tolerant performance of circuit under test quickly,increase the efficiency of finding design flaws and strengthening the circuit,and have important application value for improving the safety and stability of integrated circuits.