IPSec加密芯片中AES加密核的设计与FPGA实现

Design and FPGA Implementation of AES Encryption Chip for IPSec

中文关键词:  IPSec  AES  FPGA  两级流水线  列混合

英文关键词:IPSec  AES  FPGA  two-stage pipeline  mix-columns

中文摘要:

      为了提高IPSec加密芯片中AES加密核的数据处理速度，提出一种AES算法的FPGA改进结构。在对AES算法分析的基础上，优化了列混合运算模块，降低系统硬件资源消耗；提出两级内部流水结构，进一步缩短关键路径，提高系统运行时钟频率。仿真和实测结果表明：优化后AES核可以稳定工作于100 MHz，吞吐量提高为原来的1.5倍，达到1.24 Gb/s，显著提高了IPSec协议的处理速度，可满足千兆以太网加解密传输需求。

英文摘要:

      An improved hardware unit based on field programmable gate array (FPGA) is proposed to promote processing speed.The mixcolumn module is optimized based on the analysis of AES and the system hardware resources are reduced.Moreover,two-stage pipeline is built.Therefore,key route is shortened further.The simulation and test results show that AES core could operate stably at 100 MHz and throughout rate increases by 50%,reaching 1.24 Gb/s.Processing speed of the IPSec is improved greatly,which can meet data transmitting requirement on Gigabit Ethernet.